The fabrication processes of a semiconductor transistor are very complex processes ranging from deposition and growing of certain materials, to etching or removing certain materials, to implanting dopants at or near the source and drain regions. In the latter fabrication process, halo implantation can be provided which is a fabrication step that involves the doping of regions beneath the doped source and drain regions of the transistor so as to form halo regions. For each of such halo regions, only the portion under the gate region (called undercutting portion) is useful, and therefore desirable; whereas, the rest of the halo region has the effect of reducing the doping concentration of the respective source and drain regions, which is undesirable.
In fact, it is known that the halo regions can increase the resistance of the device, which impairs the device performance. For example, halo implants are used in CMOS fabrication to suppress punch-through effect. The halo implants are typically low energy, low current implantation processes carried out at large incident angle so that implanted dopants penetrate underneath the edge of the MOS gate stack. However, when strong halo doping is employed, there is a significant increase in junction leakage current. For many implementations, this implant also significantly increases the parasitic junction capacitance, reducing the inherent speed of the device. Also, the sheet resistance can be significantly increased, which can result in device impairment. The sheet resistance is a measure of resistance of thin films that have a uniform thickness. It is commonly used to characterize materials made by semiconductor doping, and metal deposition processes.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.